Questions
4 questions
Difficulty
Medium
Importance
Moderate yield for BHEL/NTPC
Overview
VLSI Design focuses on the integration of millions of transistors onto a single silicon chip, forming the backbone of modern digital electronics. In PSU exams, this topic tests your understanding of fabrication technologies, design abstraction levels, and timing constraints. Mastering the fundamentals of CMOS and HDL is essential for scoring in technical sections of exams like BHEL and NTPC.
CMOS Technology
CMOS (Complementary Metal Oxide Semiconductor) is the dominant fabrication technology due to its high noise immunity and low static power dissipation. Aspirants must understand the working of nMOS and pMOS transistors and their behavior as switches.
- n-channel MOSFET operates as a pull-down network (PDN).
- p-channel MOSFET operates as a pull-up network (PUN).
- Static power consumption in ideal CMOS is zero.
- Body effect increases the threshold voltage (Vth).
- Channel length modulation reduces output resistance.
Digital IC Design Flow
The design flow is a systematic approach to convert a hardware specification into a physical layout. It follows a top-down methodology involving design entry, simulation, synthesis, placement, and routing.
- Specification -> RTL -> Synthesis -> Floorplanning -> Place & Route.
- Front-end involves RTL design and functional verification.
- Back-end deals with physical layout and DRC/LVS checks.
- DRC ensures design rules are met for fabrication.
- LVS ensures the layout matches the schematic netlist.
FPGA Architecture
Field Programmable Gate Arrays are pre-fabricated silicon devices that can be configured by the user. Unlike ASICs, FPGAs provide flexibility at the cost of higher power and lower speed.
- Logic Blocks (CLBs) contain LUTs, flip-flops, and muxes.
- LUTs (Look-Up Tables) implement Boolean functions using SRAM cells.
- Interconnects are programmable routing paths.
- I/O blocks provide interface to external pins.
- FPGAs are reprogrammable, unlike Mask-ROM based ASICs.
HDL (Verilog) Basics
Verilog is a Hardware Description Language used for modeling digital systems. Exam questions often focus on the difference between concurrent and sequential statements.
- Continuous assignment uses the 'assign' keyword.
- Always blocks are used for sequential or combinational logic.
- Blocking (=) vs Non-blocking (<=) assignment types.
- Non-blocking assignments are essential for modeling registers.
- Module instantiation allows hierarchical design.
Formula Sheet
Id = kn * (Vgs - Vt)^2 (Saturation region)
P_dynamic = C * Vdd^2 * f
V_out = V_in (Inverter logic constraint)
Exam Tip
Focus on the logic circuit realization using CMOS pull-up and pull-down networks, as this is a frequent source of calculation-based questions.
Common Mistakes
- Confusing blocking and non-blocking assignment behavior in Verilog simulation.
- Ignoring the impact of body effect on threshold voltage calculations.
- Assuming all FPGA logic is implemented via gates instead of Look-Up Tables (LUTs).
More Revision Notes
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