Questions
6 questions per paper
Difficulty
Medium
Importance
High yield for HPCL/NTPC
Overview
Computer Organization and Architecture (COA) provides the structural foundation for how computing systems execute instructions and manage data. It is a high-yield topic for Indian PSU exams, requiring a deep understanding of hardware-software interaction and efficient computational design.
Number Systems & Boolean Algebra
This subtopic forms the basis of binary data representation and digital logic simplification. Candidates must master radix conversion and the application of Boolean laws to reduce complex digital expressions to their minimal form.
- Base conversion: Binary, Octal, Decimal, Hexadecimal
- De Morgan's Laws: (A+B)' = A'B' and (AB)' = A'+B'
- Boolean minimization using K-Maps
- Canonical forms: SOP and POS expressions
Logic Gates & Circuits
Logic gates are the primitive building blocks of digital electronic circuits. PSU exams frequently test your ability to analyze truth tables and determine the output of sequential or combinational logic circuits like Multiplexers and Encoders.
- Universal gates: NAND and NOR
- Combinational circuits: Adder, Subtractor, Decoder, MUX
- Sequential circuits: Flip-flops (SR, JK, D, T), Latches
- Race-around condition in JK flip-flops
CPU Architecture & Pipelining
Understanding the CPU cycle and instruction execution is critical for analyzing system performance. Pipelining concepts, specifically structural, data, and control hazards, are frequent targets for numerical-based MCQ questions in exams like NTPC and BHEL.
- Instruction Cycle: Fetch, Decode, Execute
- Pipeline performance: Speedup ratio = T_nonpipeline / T_pipeline
- Addressing modes: Immediate, Direct, Register, Indirect
- RISC vs CISC architectural trade-offs
Memory Hierarchy
Memory hierarchy addresses the trade-off between speed, cost, and capacity in system design. Aspirants should focus on cache mapping techniques and the calculation of Effective Access Time.
- Hierarchy levels: Registers, Cache, Main Memory, Secondary Storage
- Mapping techniques: Direct, Associative, Set-Associative
- Locality of Reference: Temporal and Spatial
- Effective Access Time formula: H*Tc + (1-H)*Tm
Formula Sheet
Speedup = (n * k) / (k + n - 1)
Effective Memory Access Time = H * T_cache + (1 - H) * T_main
Boolean XOR identity: A ⊕ B = AB' + A'B
Exam Tip
Prioritize solving K-Map problems and Pipeline performance metrics, as these are the most predictable 'scored' marks in PSU technical papers.
Common Mistakes
- Miscalculating the pipeline speedup ratio by ignoring the 'k' clock cycles for non-pipelined execution.
- Forgetting to verify the 'Don't Care' conditions when simplifying Boolean expressions using K-Maps.
- Confusing the different cache mapping addressing schemes during high-speed calculations.
More Revision Notes
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