Questions
3–5 questions per university paper
Difficulty
Medium
Importance
High yield for University Theory and GATE
Overview
Memory hierarchy categorizes computer memory based on speed, cost, and capacity, bridging the performance gap between the CPU and main memory. Understanding this topic is critical for computer architecture exams, as it forms the theoretical basis for optimizing system performance via cache locality.
Memory Hierarchy Structure
The memory hierarchy is organized as a pyramid structure where memory speed and cost per bit decrease from top to bottom, while capacity increases. The primary goal is to provide the processor with fast access to instructions and data using the principle of locality.
- CPU Registers are the fastest and smallest memory.
- Cache memory serves as a buffer between the CPU and Main Memory.
- Main Memory (RAM) holds active programs and data.
- Secondary storage (HDD/SSD) provides large, non-volatile capacity.
- Principle of Locality: Temporal locality and Spatial locality.
Cache Mapping Techniques
Cache mapping determines how data from main memory is placed into cache slots to ensure quick retrieval. Students must differentiate between Direct, Associative, and Set-Associative mapping methods.
- Direct Mapping: Each main memory block maps to only one specific cache line.
- Associative Mapping: Any block can reside in any cache line.
- Set-Associative Mapping: A compromise splitting cache into sets of lines.
- Tag, Index, and Offset fields are used to identify memory addresses.
- Conflict miss occurs when too many blocks map to the same set.
Cache Hit and Miss Calculations
These calculations quantify the efficiency of the cache system by determining how often the processor finds data within the cache compared to main memory. Average Memory Access Time (AMAT) is the standard metric for performance analysis.
- Hit Ratio (h) = Hits / Total Accesses.
- Miss Rate = 1 - Hit Ratio.
- AMAT = Hit Time + (Miss Rate * Miss Penalty).
- Performance improves as Miss Rate decreases.
- Miss Penalty is the extra time required to fetch data from main memory.
Formula Sheet
AMAT = Hit_Time + (Miss_Rate * Miss_Penalty)
Hit_Ratio = Number_of_Hits / (Number_of_Hits + Number_of_Misses)
Address_Format = Tag_bits + Index_bits + Offset_bits
Exam Tip
Always draw the block diagram of the Memory Hierarchy; it is a guaranteed way to score full marks in descriptive architecture questions.
Common Mistakes
- Confusing the roles of temporal and spatial locality in cache optimization.
- Incorrectly calculating the tag and index bits in direct mapping address formats.
- Failing to account for miss penalty when calculating total memory access time.
More Revision Notes
Ready to test yourself?
Play topic-wise Memory Hierarchy & Cache questions in Aspirant Arcade — gamified MCQ practice.
Download Free