Questions
1–2 descriptive questions per university paper
Difficulty
Medium
Importance
High yield for COA core theory exams
Overview
The Instruction Cycle represents the fundamental sequence of steps a CPU takes to execute a program, serving as the heartbeat of computer architecture. Mastering this process and the underlying Control Unit design is crucial, as it explains how software instructions are physically translated into hardware actions, forming a high-yield conceptual foundation for both university exams and technical interviews.
The Instruction Cycle (Fetch-Decode-Execute)
The instruction cycle is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction requires, and carries out those actions. This cycle repeats continuously from boot-up until the system is powered down, ensuring sequential program execution.
- Fetch: PC loads the instruction address, moves it to IR via MAR and MDR.
- Decode: Control Unit interprets the opcode and identifies the required operations.
- Execute: ALU performs the operation and writes back the result to memory or registers.
- PC Incrementation: PC is updated to point to the next sequential instruction address.
- Interrupt Cycle: An optional phase to handle pending hardware or software interrupts.
Hardwired Control Unit
A hardwired control unit implements the control logic using fixed logic gates, flip-flops, and encoders. It is inherently faster than microprogrammed units because it relies on combinational circuits, making it ideal for RISC architectures where instructions are simple and execution speed is critical.
- Implemented using combinational logic circuits.
- Fast execution speed due to lack of memory access for control signals.
- Difficult to modify or upgrade once the physical design is finalized.
- Expensive to design for complex instruction sets (CISC).
- Uses a fixed state machine to generate control signals.
Microprogrammed Control Unit
Microprogrammed control units manage instructions by storing control sequences in a special memory called Control Memory. By treating instructions as a series of micro-operations stored in control words, this design offers high flexibility, allowing complex instruction sets to be updated easily via software changes.
- Control signals are stored as microinstructions in Control Memory (ROM).
- Highly flexible and easier to implement for complex instruction sets.
- Slower performance due to the need to access Control Memory (ROM latency).
- Uses a Control Address Register (CAR) to sequence through micro-instructions.
- Preferred for CISC architectures like x86.
Formula Sheet
T_cycle = T_fetch + T_decode + T_execute + T_writeback
PC_next = PC_current + Instruction_Length
Exam Tip
When comparing Hardwired vs Microprogrammed control, always emphasize speed versus flexibility; hardwired wins on speed, microprogrammed wins on adaptability.
Common Mistakes
- Confusing the order of the Fetch-Decode-Execute cycle phases.
- Assuming Hardwired control units can be easily updated after manufacturing.
- Neglecting the role of the Program Counter (PC) and its automatic increment logic.
More Revision Notes
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