Questions
3-4 questions in semester exams
Difficulty
Medium
Importance
High yield for University Semester Exams
Overview
CPU and ALU design forms the bedrock of computer architecture, focusing on how instructions are processed, stored, and executed. Understanding these components is critical for semester exams as they bridge the gap between abstract software commands and physical hardware execution.
Register Organization
Registers are high-speed, temporary storage locations inside the CPU that facilitate rapid data access and instruction execution. They are classified based on their role in storing addresses, status flags, or general-purpose data operands.
- Accumulator (AC) stores intermediate results
- Program Counter (PC) holds address of next instruction
- Memory Address Register (MAR) communicates with memory bus
- Instruction Register (IR) holds current instruction to be decoded
- Flag Register (Status Register) monitors CPU state (Zero, Carry, Overflow)
ALU Operations
The Arithmetic Logic Unit (ALU) is the primary combinatorial circuit within the CPU responsible for performing arithmetic and bitwise logic operations. It functions as the computational engine governed by control signals from the control unit.
- Performs arithmetic (Addition, Subtraction)
- Performs logical operations (AND, OR, NOT, XOR)
- Operates on operands fetched from registers
- Output is stored in the Accumulator or written to memory
- Generates status flags like Zero, Carry, and Negative
Instruction Set Architecture (ISA)
ISA defines the abstract interface between the hardware and the software, specifying the set of instructions the CPU can understand. It encompasses the instruction format, addressing modes, and the opcode-operand structure.
- Zero-address instruction (Stack-based)
- One-address instruction (Implied accumulator)
- Two-address instruction (Source and destination register)
- Three-address instruction (Two sources and one destination)
- Addressing modes like Immediate, Direct, and Indirect
- Opcode defines the operation, operand defines the data location
Exam Tip
Always draw the block diagram of the CPU data path when asked about instruction cycles; visual representations earn significantly higher marks than text alone.
Common Mistakes
- Confusing the function of the PC with the MAR during the fetch cycle
- Failing to explain the role of Status Flags in conditional branching
- Interchanging the definitions of RISC and CISC architectures in instruction design
More Revision Notes
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